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            <h1 class="post-title">FPGA学习笔记(四)——Verilog HDL条件语句与循环语句</h1>
            
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                        Author: <a itemprop="author" rel="author" href="/about/">WD</a>
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                        <span class="post-time">
                        Date: <a href="#">October 17, 2019&nbsp;&nbsp;21:09:32</a>
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                                <a href="/categories/FPGA/">FPGA</a>
                            
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            <h2 id="1-if—else语句"><a href="#1-if—else语句" class="headerlink" title="1.if—else语句"></a>1.if—else语句</h2><ul>
<li><p>其格式与C语言中的if—else语句类似，使用方法有以下3种：</p>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br><span class="line">16</span><br><span class="line">17</span><br><span class="line">18</span><br><span class="line">19</span><br><span class="line">20</span><br><span class="line">21</span><br><span class="line">22</span><br><span class="line">23</span><br></pre></td><td class="code"><pre><span class="line"><span class="comment">//形式1：只有if的形式</span></span><br><span class="line"><span class="keyword">if</span>(表达式)  语句<span class="number">1</span>;</span><br><span class="line"><span class="keyword">if</span>(表达式)</span><br><span class="line">    <span class="keyword">begin</span></span><br><span class="line">        表达式<span class="number">1</span>;</span><br><span class="line">    <span class="keyword">end</span></span><br><span class="line"><span class="comment">//形式2：if--else形式</span></span><br><span class="line"><span class="keyword">if</span>(表达式)</span><br><span class="line">    语句或语句块<span class="number">1</span>;</span><br><span class="line"><span class="keyword">else</span></span><br><span class="line">    语句或语句块<span class="number">2</span>;</span><br><span class="line"><span class="comment">//形式3：if--else嵌套形式</span></span><br><span class="line"><span class="keyword">if</span> ( 表达式<span class="number">1</span>)    语句<span class="number">1</span>;     </span><br><span class="line"><span class="keyword">else</span> <span class="keyword">if</span> ( 表达式<span class="number">2</span> )  语句<span class="number">2</span>;</span><br><span class="line"><span class="keyword">else</span> <span class="keyword">if</span> ( 表达式<span class="number">3</span> )  语句<span class="number">3</span>;</span><br><span class="line">........</span><br><span class="line"><span class="keyword">else</span> <span class="keyword">if</span> ( 表达式m )  语句m;</span><br><span class="line"><span class="keyword">else</span>               语句n;</span><br><span class="line"><span class="comment">//例如：</span></span><br><span class="line"><span class="keyword">if</span> ( a &gt; b )      out = int1;</span><br><span class="line"><span class="keyword">else</span> <span class="keyword">if</span> ( a == b)  out1= int2;</span><br><span class="line"><span class="keyword">else</span>           out1 = int3; </span><br><span class="line"></span><br></pre></td></tr></table></figure>
</li>
<li><p>表达式：一般为逻辑表达式或关系表达式，也可能是一位的变量。</p>
</li>
<li><p>系统对表达式的值进行判断，若为0，x，z，按“假”处理；若为1，按“真”处理，执行指定语句。</p>
</li>
<li><p>语句可是单句，也可是多句，多句时用“begin - end”语句括起来。对于if语句的嵌套，若不清楚if和else的匹配，最好用begin-end语句括起来。</p>
</li>
<li><p>条件语句必须在过程块中使用：</p>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br></pre></td><td class="code"><pre><span class="line"><span class="keyword">always</span>@(a,b,int1,int2) </span><br><span class="line">     <span class="keyword">begin</span></span><br><span class="line">    <span class="keyword">if</span>(a&gt;b)</span><br><span class="line">        <span class="keyword">begin</span>      </span><br><span class="line">            out1=int1;     </span><br><span class="line">            out2=int2;        </span><br><span class="line">        <span class="keyword">end</span></span><br><span class="line">    <span class="keyword">else</span></span><br><span class="line">       <span class="keyword">begin</span>       </span><br><span class="line">           out1=int2;       </span><br><span class="line">           out2=int1;      </span><br><span class="line">       <span class="keyword">end</span></span><br><span class="line"> <span class="keyword">end</span></span><br></pre></td></tr></table></figure>
</li>
<li><p>允许一定形式的表达式简写方式：</p>
<p><code>if(expression) 等同于  if(expression == 1)</code></p>
<p><code>if(!expression)  等同于 if(expression!= 1)</code></p>
</li>
<li><p>if语句的嵌套,即在if语句中又包含一个或多个if语句称为if语句的嵌套。应当注意if与else的配对关系，else总是与它上面的最近的if配对。</p>
</li>
<li><p>if-else 嵌套形式隐含优先级关系：</p>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br></pre></td><td class="code"><pre><span class="line"><span class="keyword">always</span>@(sela <span class="keyword">or</span> selb <span class="keyword">or</span> a <span class="keyword">or</span> b <span class="keyword">or</span> c)</span><br><span class="line">   <span class="keyword">begin</span></span><br><span class="line">     <span class="keyword">if</span>(sela)  q=a;</span><br><span class="line">     <span class="keyword">else</span> <span class="keyword">if</span>(selb) q=b;</span><br><span class="line">      <span class="keyword">else</span> q=c;</span><br><span class="line">   <span class="keyword">end</span></span><br></pre></td></tr></table></figure>
<p><img src="https://img-blog.csdnimg.cn/20191017211255541.PNG?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3FxXzQwMTgxNTky,size_16,color_FFFFFF,t_70" alt=""></p>
</li>
</ul>
<h2 id="2-case语句"><a href="#2-case语句" class="headerlink" title="2.case语句"></a>2.case语句</h2><ul>
<li><p>Verilog语言提供的case语句直接处理多分支选择，通常用于描述译码器、数据选择器、状态机及微处理器的指令译码等，它的一般形式如下:</p>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br></pre></td><td class="code"><pre><span class="line"><span class="keyword">case</span>(表达式)</span><br><span class="line">    分支表达式<span class="number">1</span>：语句<span class="number">1</span>;</span><br><span class="line">    分支表达式<span class="number">2</span>：语句<span class="number">2</span>;</span><br><span class="line">    ···</span><br><span class="line">    分支表达式n：语句n;</span><br><span class="line">    <span class="keyword">default</span>: 语句n+<span class="number">1</span>; <span class="comment">//如果前面列出了表达式所有可能取值，default语句可以省略</span></span><br><span class="line"><span class="keyword">endcase</span>      </span><br></pre></td></tr></table></figure>
</li>
<li><p><strong>case</strong>括弧内的表达式称为控制表达式，case分支项中的表达式称为分支表达式。分支表达式则用这些控制信号的具体状态值来表示，因此分支表达式又可以称为常量表达式。</p>
</li>
<li><p>当控制表达式的值与分支表达式的值相等时，就执行分支表达式后面的语句；如果所有的分支表达式的值都没有与控制表达式的值相匹配，就执行default后面的语句。</p>
</li>
<li><p>分支表达式后面的语句也可以是由begin-end括起来的语句块。</p>
</li>
<li><p>default项可有可无，一个case语句里只准有一个default项。同样，case也只能在块语句中使用。</p>
</li>
</ul>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br><span class="line">16</span><br><span class="line">17</span><br></pre></td><td class="code"><pre><span class="line"><span class="comment">//case语句实现3-8译码器的部分代码如下：</span></span><br><span class="line">     <span class="keyword">wire</span>[<span class="number">2</span>:<span class="number">0</span>] sel;</span><br><span class="line">     <span class="keyword">reg</span>[<span class="number">7</span>:<span class="number">0</span>]  res;</span><br><span class="line">     <span class="keyword">always</span> @ (sel <span class="keyword">or</span> res)</span><br><span class="line">      <span class="keyword">begin</span></span><br><span class="line"><span class="comment">//case语句;</span></span><br><span class="line">  <span class="keyword">case</span> (sel)</span><br><span class="line">       <span class="number">3</span>’b000 : res=<span class="number">8</span>’b00000001;</span><br><span class="line">       <span class="number">3</span>’b001 : res=<span class="number">8</span>’b00000010;</span><br><span class="line">       <span class="number">3</span>’b010 : res=<span class="number">8</span>’b00000100;</span><br><span class="line">       <span class="number">3</span>’b011 : res=<span class="number">8</span>’b00001000;</span><br><span class="line">       <span class="number">3</span>’b100 : res=<span class="number">8</span>’b00010000;</span><br><span class="line">       <span class="number">3</span>’b101:  res=<span class="number">8</span>’b00100000;</span><br><span class="line">       <span class="number">3</span>’b110 : res=<span class="number">8</span>’b01000000;</span><br><span class="line">       <span class="keyword">default</span>:  res=<span class="number">8</span>’b10000000;</span><br><span class="line">   <span class="keyword">endcase</span></span><br><span class="line"> <span class="keyword">end</span></span><br></pre></td></tr></table></figure>
<ul>
<li><p>case语句的所有表达式值的位宽必须相等，只有这样，控制表达式和分支表达式才能进行对应位的比较。一个经常犯的错误是用’bx,’bz来替代n’bx,n’bz，这样写是不对的，因为信号x,z的默认宽度是机器的字节宽度，通常是32位。</p>
</li>
<li><p>执行完case分项后的语句，则跳出该case语句结构，终止case语句的执行。</p>
</li>
<li><p>在case语句中，表达式与分支表达式1到分支表达式n之间的比较是一种全等比较（<strong>===</strong>），必须保证两者的对应位全等。如果表达式的值和分支表达式的值同时为不定值或者同时为高阻态，则认为是相等的</p>
<p>| case | 0    | 1    | x    | z    |<br>| —— | —— | —— | —— | —— |<br>| 0    | 1    | 0    | 0    | 0    |<br>| 1    | 0    | 1    | 0    | 0    |<br>| x    | 0    | 0    | 1    | 0    |<br>| z    | 0    | 0    | 0    | 1    |</p>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br></pre></td><td class="code"><pre><span class="line"><span class="keyword">case</span> ( a )</span><br><span class="line">     <span class="number">2</span>’b1x:out = <span class="number">1</span>;   <span class="comment">// 只有a = 1x,才有out = 1</span></span><br><span class="line">     <span class="number">2</span>’b1z:out = <span class="number">0</span>;    <span class="comment">// 只有a = 1z,才有out = 0</span></span><br><span class="line">   ...</span><br><span class="line"><span class="keyword">endcase</span></span><br></pre></td></tr></table></figure>
</li>
<li><p>```verilog<br>case(select[1,2])</p>
<pre><code> 2&#39;b00: result   = 0;
 2&#39;b01: result   = flaga;
 2&#39;b0x,
 2&#39;b0z: result   = flaga ? &#39;bx:0;
 2&#39;b10: result   = flagb;
 2&#39;bx0，
 2&#39;bz0: result   = 0;
default: result   = flagb ? &#39;bz:0;
</code></pre><p> endcase<br>//当多个分项可以共用一个语句或语句块。其分支表达式之间用“，”隔开。</p>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br><span class="line">16</span><br><span class="line">17</span><br><span class="line">18</span><br><span class="line">19</span><br><span class="line">20</span><br><span class="line">21</span><br><span class="line">22</span><br><span class="line">23</span><br><span class="line">24</span><br><span class="line">25</span><br><span class="line">26</span><br></pre></td><td class="code"><pre><span class="line"></span><br><span class="line">- case语句还有两种变种，即casez语句和casex语句。 </span><br><span class="line"></span><br><span class="line">- casez：</span><br><span class="line"></span><br><span class="line">  ​    忽略比较过程中值为z的位，即如果比较的双方（表达式的值与分支表达式的值）有一方的某一位的值是z，那么对这些位的比较就不予考虑，只需关注其他位的比较结果。</span><br><span class="line"></span><br><span class="line">- casex:</span><br><span class="line"></span><br><span class="line">  ​    在casex语句中，则把这种处理方式进一步扩展到对x的处理，即将z和x均视为无关值。</span><br><span class="line"></span><br><span class="line">  | casez | 0    | 1    | x    | z    |</span><br><span class="line">  | ----- | ---- | ---- | ---- | ---- |</span><br><span class="line">  | 0     | 1    | 0    | 0    | 1    |</span><br><span class="line">  | 1     | 0    | 1    | 0    | 1    |</span><br><span class="line">  | x     | 0    | 0    | 1    | 1    |</span><br><span class="line">  | z     | 1    | 1    | 1    | 1    |</span><br><span class="line"></span><br><span class="line">  ```verilog</span><br><span class="line">  //在分支表达式中，z常用？代替。</span><br><span class="line">  casez(a)</span><br><span class="line">           3&#x27;b1?? :  out1 = 1;//如果a=100、101、110、111或1xx,1zz等，都有out1 = 1。</span><br><span class="line">       </span><br><span class="line">           3&#x27;b0?1 :  out2 = 1; //如果a=001、011、0x1、0z1，都有out2 = 1</span><br><span class="line">          .......</span><br><span class="line">  endcase</span><br></pre></td></tr></table></figure>
<p>| casex | 0    | 1    | x    | z    |<br>| ——- | —— | —— | —— | —— |<br>| 0     | 1    | 0    | 1    | 1    |<br>| 1     | 0    | 1    | 1    | 1    |<br>| x     | 1    | 1    | 1    | 1    |<br>| z     | 1    | 1    | 1    | 1    |</p>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br></pre></td><td class="code"><pre><span class="line">例如：</span><br><span class="line">    <span class="keyword">casex</span>(a)</span><br><span class="line">	         <span class="number">2&#x27;b1x</span>:out=<span class="number">1</span>;  </span><br><span class="line">          ..................</span><br><span class="line">     <span class="keyword">endcase</span></span><br><span class="line"><span class="comment">//如果a=10、11、1x、1z，都有out=1。</span></span><br></pre></td></tr></table></figure>
</li>
<li><p>if语句条件不完备情况</p>
<p>如果if语句和case语句的条件描述不完备，会造成不必要的锁存器 。</p>
<p>一般不可能列出所有分支，因为每一变量至少有4种取值0，1，z，x。为包含所有分支，可在if语句最后加上else；在case语句的最后加上default语句。 </p>
</li>
<li><p>回顾一下锁存器和寄存器的区别：</p>
<p><img src="https://img-blog.csdnimg.cn/20191017211315546.PNG?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3FxXzQwMTgxNTky,size_16,color_FFFFFF,t_70" alt=""></p>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br></pre></td><td class="code"><pre><span class="line"><span class="keyword">always</span>@(a <span class="keyword">or</span> b) </span><br><span class="line">        <span class="keyword">begin</span> </span><br><span class="line">           <span class="keyword">if</span>(a == <span class="number">1</span>’b1)</span><br><span class="line">                y = b;</span><br><span class="line">       <span class="keyword">end</span></span><br></pre></td></tr></table></figure>
<p><img src="https://img-blog.csdnimg.cn/20191017211324396.PNG?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3FxXzQwMTgxNTky,size_16,color_FFFFFF,t_70" alt=""></p>
</li>
</ul>
  <figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br></pre></td><td class="code"><pre><span class="line"><span class="keyword">always</span>@(<span class="keyword">posedge</span> clk) </span><br><span class="line">        <span class="keyword">begin</span> </span><br><span class="line">          <span class="keyword">if</span>(a == <span class="number">1</span>’b1)</span><br><span class="line">              y &lt;= b;</span><br><span class="line">       <span class="keyword">end</span></span><br><span class="line"><span class="comment">//毛刺通过D触发器被滤除</span></span><br></pre></td></tr></table></figure>
<p>  <img src="https://img-blog.csdnimg.cn/20191017211333197.PNG?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3FxXzQwMTgxNTky,size_16,color_FFFFFF,t_70" alt=""></p>
<p>  <img src="https://img-blog.csdnimg.cn/20191017211340563.PNG?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3FxXzQwMTgxNTky,size_16,color_FFFFFF,t_70" alt=""></p>
<ul>
<li><p>对FPGA来说，它的基本逻辑单元由多输入查找表、 D触发器构成，并不存在锁存器结构，因此如果在FPGA设计中使用锁存器，需要更多的资源来搭建锁存器，反而会更消耗资源。</p>
</li>
<li><p>所以在FPGA设计中，应该避免锁存器。在时序逻辑电路中，可以将锁存器改为带使能端的D触发器；在组合电路中，可以通过更改代码以覆盖所有条件分支等方式避免产生锁存器。</p>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br></pre></td><td class="code"><pre><span class="line"> <span class="keyword">always</span> @(al <span class="keyword">or</span> d)</span><br><span class="line">    <span class="keyword">begin</span></span><br><span class="line">     <span class="keyword">if</span>(al)</span><br><span class="line">          q&lt;=d;</span><br><span class="line">    <span class="keyword">end</span></span><br><span class="line">    <span class="comment">//有锁存器</span></span><br><span class="line"><span class="keyword">always</span> @(al <span class="keyword">or</span> d)</span><br><span class="line">  <span class="keyword">begin</span></span><br><span class="line">    <span class="keyword">if</span>(al)   q&lt;=d;</span><br><span class="line">    <span class="keyword">else</span>    q&lt;=<span class="number">0</span></span><br><span class="line">  <span class="keyword">end</span></span><br><span class="line">    <span class="comment">//无锁存器</span></span><br></pre></td></tr></table></figure>
</li>
<li><p>检查一下上边的”always”块，if语句保证了只有当al=1时，q才取d的值。这段程序没有写出 al = 0 时的结果, 那么当al=0时会怎么样呢？</p>
<p>在”always”块内，如果在给定的条件下变量没有赋值，这个变量将保持原值，也就是说会生成一个锁存器！ </p>
</li>
<li><p>避免偶然生成锁存器的错误。如果用到if语句，最好写上else项。如果用case语句，最好写上default项。遵循上面两条原则，就可以避免发生这种错误，使设计者更加明确设计目标，同时也增强了Verilog程序的可读性。</p>
</li>
</ul>
<h2 id="3-forever语句"><a href="#3-forever语句" class="headerlink" title="3.forever语句"></a>3.forever语句</h2><figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br></pre></td><td class="code"><pre><span class="line"><span class="keyword">forever</span>语句的格式如下：</span><br><span class="line">      <span class="keyword">forever</span>   语句;</span><br><span class="line">    或者：    </span><br><span class="line">       <span class="keyword">forever</span></span><br><span class="line">          <span class="keyword">begin</span>            </span><br><span class="line">              语句<span class="number">1</span>;</span><br><span class="line">              语句<span class="number">2</span>;</span><br><span class="line">              ……</span><br><span class="line">          <span class="keyword">end</span></span><br></pre></td></tr></table></figure>
<ul>
<li><p>forever表示永久循环，无条件地无限次执行其后的语句，相当于while(1),直到遇到系统任务<code>$finish</code>或<code>$stop</code>,如果需要从循环中退出，可以使用<code>disable</code>。</p>
</li>
<li><p>循环语句多用于生成时钟等周期性波形，它与always语句不同之处在于不能独立写在程序中，而必须写在initial块中。</p>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br></pre></td><td class="code"><pre><span class="line"><span class="keyword">initial</span></span><br><span class="line">    <span class="keyword">begin</span></span><br><span class="line">         clk = <span class="number">0</span>;</span><br><span class="line">         <span class="keyword">forever</span> #<span class="number">25</span> clk = ~clk;     </span><br><span class="line">    <span class="keyword">end</span></span><br></pre></td></tr></table></figure>
</li>
<li><p>forever应该是过程块中最后一条语句。其后的语句将永远不会执行。</p>
</li>
<li><p>forever语句不可综合，通常用于testbench描述。</p>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br></pre></td><td class="code"><pre><span class="line">...</span><br><span class="line"><span class="keyword">reg</span> clk;</span><br><span class="line"><span class="keyword">initial</span></span><br><span class="line">      <span class="keyword">begin</span></span><br><span class="line">      clk = <span class="number">0</span>;</span><br><span class="line">      <span class="keyword">forever</span> <span class="comment">//这种行为描述方式可以非常灵活的描述时钟，可以控制时钟的开始时间及周期占空比。仿真效率也高。</span></span><br><span class="line">            <span class="keyword">begin</span></span><br><span class="line">                 #<span class="number">10</span> clk = <span class="number">1</span>;</span><br><span class="line">                 #<span class="number">10</span> clk = <span class="number">0</span>;</span><br><span class="line">           <span class="keyword">end</span></span><br><span class="line"><span class="keyword">end</span></span><br><span class="line">...</span><br></pre></td></tr></table></figure>
</li>
</ul>
<h2 id="4-repeat语句"><a href="#4-repeat语句" class="headerlink" title="4.repeat语句"></a>4.repeat语句</h2><ul>
<li><p>repeat语句是最简单的循环语句，用于循环次数已知的情况。</p>
<p>repeat语句的表达形式为：</p>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br></pre></td><td class="code"><pre><span class="line"><span class="keyword">repeat</span>（循环次数）</span><br><span class="line">     <span class="keyword">begin</span></span><br><span class="line">         操作<span class="number">1</span>；</span><br><span class="line">	     操作<span class="number">2</span>；</span><br><span class="line">         ………</span><br><span class="line">     <span class="keyword">end</span></span><br></pre></td></tr></table></figure>
</li>
<li><p>下例实现连续8次循环左移的操作：       </p>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br></pre></td><td class="code"><pre><span class="line"><span class="keyword">if</span> (rotate == <span class="number">1</span>)</span><br><span class="line">  <span class="keyword">repeat</span> (<span class="number">8</span>)     </span><br><span class="line">   <span class="keyword">begin</span></span><br><span class="line">       temp = data[<span class="number">15</span>];</span><br><span class="line">       data = &#123;data &lt;&lt; <span class="number">1</span>,temp&#125;;  <span class="comment">// data循环左移8次</span></span><br><span class="line">   <span class="keyword">end</span></span><br></pre></td></tr></table></figure>
</li>
</ul>
<h2 id="5-while语句"><a href="#5-while语句" class="headerlink" title="5.while语句"></a>5.while语句</h2><ul>
<li><p>while语句通过控制某个变量的取值来控制循环次数。一般表达形式：</p>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br></pre></td><td class="code"><pre><span class="line"><span class="keyword">while</span>(条件)</span><br><span class="line">    <span class="keyword">begin</span></span><br><span class="line">          操作<span class="number">1</span>；</span><br><span class="line">          操作<span class="number">2</span>；</span><br><span class="line">          ………</span><br><span class="line">     <span class="keyword">end</span></span><br></pre></td></tr></table></figure>
<p>  在使用while语句时，一般在循环体内更新条件的取值，以保证在适当的时候退出循环。</p>
</li>
<li><p>下例实现连续4次循环的操作</p>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br></pre></td><td class="code"><pre><span class="line">i = <span class="number">0</span>;</span><br><span class="line"><span class="keyword">while</span>(i &lt; <span class="number">4</span>)</span><br><span class="line">    <span class="keyword">begin</span></span><br><span class="line">       a = a + <span class="number">1</span>;</span><br><span class="line">       <span class="comment">//更新条件取值，使循环4次退出循环</span></span><br><span class="line"> 	   i = i + <span class="number">1</span>; </span><br><span class="line">    <span class="keyword">end</span></span><br></pre></td></tr></table></figure>
</li>
<li><p>可见在while结构中只要表达式为真(不为0)，则重复执行一条语句(或语句块)</p>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br><span class="line">16</span><br><span class="line">17</span><br><span class="line">18</span><br><span class="line">19</span><br><span class="line">20</span><br><span class="line">21</span><br><span class="line">22</span><br></pre></td><td class="code"><pre><span class="line"><span class="comment">//其功能为：统计tempreg中 1 的个数</span></span><br><span class="line">. . .</span><br><span class="line"><span class="keyword">reg</span> [<span class="number">7</span>: <span class="number">0</span>] tempreg;</span><br><span class="line"><span class="keyword">reg</span> [<span class="number">3</span>: <span class="number">0</span>] count;</span><br><span class="line">. . .</span><br><span class="line">      count = <span class="number">0</span>;</span><br><span class="line">      <span class="keyword">while</span> (tempreg) </span><br><span class="line">      <span class="keyword">begin</span></span><br><span class="line">            <span class="keyword">if</span> (tempreg[<span class="number">0</span>]) </span><br><span class="line">                count = count + <span class="number">1</span>;</span><br><span class="line">            tempreg = tempreg &gt;&gt; <span class="number">1</span>; <span class="comment">// Shift right</span></span><br><span class="line">      <span class="keyword">end</span></span><br><span class="line"><span class="keyword">end</span></span><br><span class="line">. . .</span><br><span class="line"><span class="comment">/*</span></span><br><span class="line"><span class="comment">Tempreg：</span></span><br><span class="line"><span class="comment"> 1011</span></span><br><span class="line"><span class="comment"> 0101</span></span><br><span class="line"><span class="comment"> 0010</span></span><br><span class="line"><span class="comment"> 0001</span></span><br><span class="line"><span class="comment"> 0000</span></span><br><span class="line"><span class="comment">*/</span></span><br></pre></td></tr></table></figure>
</li>
</ul>
<h2 id="6-for语句"><a href="#6-for语句" class="headerlink" title="6.for语句"></a>6.for语句</h2><ul>
<li><p>for语句可以实现所有的循环结构。其表达形式如下：</p>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br></pre></td><td class="code"><pre><span class="line"><span class="keyword">for</span>(循环变量赋初值；条件表达式；更新循环变量)</span><br><span class="line">       <span class="keyword">begin</span></span><br><span class="line">          操作<span class="number">1</span>：</span><br><span class="line">          操作<span class="number">2</span>；</span><br><span class="line">          ………</span><br><span class="line">       <span class="keyword">end</span></span><br></pre></td></tr></table></figure>
</li>
<li><p>它的执行过程如下:</p>
<p>(1)先对循环变量赋初值。</p>
<p>(2)计算条件表达式，若其值为真(非0)，则执行for语句中指定的内嵌语句，然后执行下面的第(3)步。若为假(0)，则结束循环，转到第5步。</p>
<p>(3) 若条件表达式为真，在执行指定的语句后，执行更新循环变量。</p>
<p>(4) 转回上面的第(2)步骤继续执行。</p>
<p>(5) 执行for语句下面的语句。</p>
</li>
</ul>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br></pre></td><td class="code"><pre><span class="line"><span class="keyword">for</span>(i = <span class="number">0</span>; i &lt;<span class="number">4</span>; i =i+<span class="number">1</span>)</span><br><span class="line">    <span class="keyword">begin</span> </span><br><span class="line">		a = a+<span class="number">1</span>;</span><br><span class="line">     <span class="keyword">end</span></span><br></pre></td></tr></table></figure>
<ul>
<li><p>例：用for语句来实现8位数据中低4位左移到高4位；</p>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br></pre></td><td class="code"><pre><span class="line"> <span class="keyword">integer</span> i;</span><br><span class="line"> <span class="keyword">reg</span> [<span class="number">7</span>:<span class="number">0</span>] datain;</span><br><span class="line">  </span><br><span class="line"><span class="keyword">always</span> @ (<span class="keyword">posedge</span> clk)</span><br><span class="line">  <span class="keyword">begin</span></span><br><span class="line">       <span class="keyword">for</span>(i=<span class="number">4</span>;i&lt;=<span class="number">7</span>;i=i+<span class="number">1</span>)</span><br><span class="line">           <span class="keyword">begin</span></span><br><span class="line">              datain[i]  &lt;=  datain [i-<span class="number">4</span>];</span><br><span class="line">           <span class="keyword">end</span></span><br><span class="line">  <span class="keyword">end</span>　　　</span><br></pre></td></tr></table></figure>
</li>
<li><p>例：编写 在一个时钟周期内用for语句计算出13路脉冲信号为高电平的个数。</p>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br></pre></td><td class="code"><pre><span class="line"> <span class="keyword">input</span> clk,rst;</span><br><span class="line"> <span class="keyword">input</span> [<span class="number">12</span>:<span class="number">0</span>]  datain;    </span><br><span class="line"> <span class="keyword">output</span> [<span class="number">3</span>:<span class="number">0</span>]  numout;    </span><br><span class="line"> <span class="keyword">reg</span> [<span class="number">3</span>:<span class="number">0</span>] i;</span><br><span class="line"> <span class="keyword">reg</span> [<span class="number">3</span>:<span class="number">0</span>] num;</span><br><span class="line"><span class="keyword">always</span> @ (<span class="keyword">posedge</span> clk) </span><br><span class="line">  <span class="keyword">begin</span></span><br><span class="line">      <span class="keyword">if</span> ( !rst )  <span class="comment">//重置信号</span></span><br><span class="line">           num &lt;= <span class="number">0</span>;  </span><br><span class="line">         <span class="keyword">else</span> </span><br><span class="line">        <span class="keyword">begin</span></span><br><span class="line">                <span class="keyword">for</span> ( i = <span class="number">0</span>; i &lt; <span class="number">13</span>; i = i + <span class="number">1</span>)   <span class="comment">//用for循环进行计算</span></span><br><span class="line">                <span class="keyword">if</span> ( datain [i ] )  num  &lt;= num +<span class="number">1</span>;                   </span><br><span class="line">             <span class="keyword">end</span></span><br><span class="line">  <span class="keyword">end</span></span><br></pre></td></tr></table></figure>
</li>
</ul>
<h2 id="7-disable语句"><a href="#7-disable语句" class="headerlink" title="7.disable语句"></a>7.disable语句</h2><ul>
<li>在有些特殊的情况下，需要使用disable强制退出循环。</li>
<li>使用disable语句强制退出循环，首先要给循环部分起个名字，方法是在begin后添加“： 名字”。即disable语句可以中止有名字的begin…end块和fork…join块。</li>
<li>语句块可以具有自己的名字，这称为命名块。</li>
</ul>
<p>命名块的特点是:</p>
<p>   命名块中可以声明局部变量;</p>
<p>   命名块是设计层次的一部分，命名块中声明的变量可以通过层次名引用进行访问</p>
<p>   命名块可以被禁用，例如停止其执行。</p>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br></pre></td><td class="code"><pre><span class="line"><span class="comment">//命名块</span></span><br><span class="line"><span class="keyword">module</span> top;</span><br><span class="line"> <span class="keyword">initial</span></span><br><span class="line">   <span class="keyword">begin</span> : block1</span><br><span class="line">      <span class="keyword">integer</span> i;</span><br><span class="line">      ……….</span><br><span class="line">    <span class="keyword">end</span></span><br><span class="line">  </span><br><span class="line"><span class="keyword">initial</span></span><br><span class="line">   <span class="keyword">fork</span> : block2</span><br><span class="line">      <span class="keyword">reg</span> i;</span><br><span class="line">      ……….</span><br><span class="line">      ……….</span><br><span class="line">    <span class="keyword">join</span></span><br></pre></td></tr></table></figure>
<ul>
<li><p>Verilog通过关键字disable提供了一种中止命名块执行的方法。</p>
<p>disable可以用来从循环中退出、处理错误条件以及根据控制信号来控制某些代码段是否被执行。</p>
<p>对块语句的禁用导致本块语句终止执行，紧接在块后面的那条语句被执行。</p>
</li>
<li><p>例：(在C语言中break和continue的区别)</p>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br></pre></td><td class="code"><pre><span class="line"><span class="keyword">begin</span>  :<span class="keyword">continue</span></span><br><span class="line">      a = <span class="number">0</span>; b =<span class="number">0</span>;</span><br><span class="line">      <span class="keyword">for</span>(i=<span class="number">0</span>;i&lt;<span class="number">4</span>;i = i+<span class="number">1</span>)</span><br><span class="line">       <span class="keyword">begin</span></span><br><span class="line">          a = a+<span class="number">1</span>;</span><br><span class="line">          <span class="keyword">if</span>(i==<span class="number">2</span>) <span class="keyword">disable</span> <span class="keyword">continue</span>;</span><br><span class="line">          b = b+<span class="number">1</span>;</span><br><span class="line">       <span class="keyword">end</span></span><br><span class="line"> <span class="keyword">end</span></span><br><span class="line"> ……………….;<span class="comment">//a做3次加1操作后强制退出循环；而b只做2次加1操作。</span></span><br></pre></td></tr></table></figure>
<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br></pre></td><td class="code"><pre><span class="line">     a=<span class="number">0</span>; </span><br><span class="line">     b=<span class="number">0</span>;</span><br><span class="line">     <span class="keyword">for</span>( i=<span class="number">0</span>; i&lt;<span class="number">4</span>; i=i+<span class="number">1</span>)</span><br><span class="line">       <span class="keyword">begin</span>: <span class="keyword">continue</span></span><br><span class="line">	    a = a+<span class="number">1</span>;</span><br><span class="line">               <span class="keyword">if</span>( i ==<span class="number">2</span>) <span class="keyword">disable</span> <span class="keyword">continue</span>;</span><br><span class="line">               b= b+<span class="number">1</span>;</span><br><span class="line">        <span class="keyword">end</span></span><br><span class="line">      ……………………….;</span><br><span class="line"><span class="comment">//中止一次循环，继续下一次循环； a做4次加1操作， b只做3次加1操作.</span></span><br></pre></td></tr></table></figure>
</li>
</ul>

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